The present invention is related in general to the field of semiconductor devices and processes and more specifically to structure, materials and fabrication of high performance plastic ball grid array packages designed for very high frequency operation.
Ball Grid Array (BGA) packages have emerged as an excellent packaging solution for integrated circuit (IC) chips with high input/output (I/O) count. BGA packages use sturdy solder balls for surface mount connection to the xe2x80x9coutside worldxe2x80x9d (typically plastic circuit boards, PCB) rather sensitive package leads, as in Quad Flat Packs (QFP), Small Outline Packages (SOP), or Tape Carrier Packages (TCP). Some BGA advantages include ease of assembly, use of surface mount process, low failure rate in PCB attach, economic use of board area, and robustness under environmental stress. The latter used to be true only for ceramic BGA packages, but has been validated in the last few years even for plastic BGAs. From the standpoint of high quality and reliability in PCB attach, BGA packages lend themselves much more readily to a six-sigma failure rate fabrication strategy than conventional devices with leads to be soldered.
A BGA package generally includes an IC chip, a multi-layer substrate, and a heat spreader. The chip is generally mounted on the heat spreader using a thermally conductive adhesive, such as an epoxy. The heat spreader provides a low resistance thermal path to dissipate thermal energy, and is thus essential for improved thermal performance during device operation, necessary for consistently good electrical performance. Further, the heat spreader provides structural and mechanical support by acting as a stiffener, adding rigidity to the BGA package, and may thus be referred to as a heat spreader/stiffener.
One of the substrate layers includes a signal xe2x80x9cplanexe2x80x9d that provides various signal lines, which can be coupled, on one end, to a corresponding chip bond pad using a wire bond (or to a contact pad using flip-chip solder connection). On the other end, the signal lines are coupled with solder xe2x80x9cballsxe2x80x9d to other circuitry, generally through a PCB. These solder balls form the array referred to in a BGA. Additionally, a ground plane will generally be included on one of the substrate layers to serve as an active ground plane to improve overall device performance by lowering the inductance, providing controlled impedance, and reducing cross talk. These features become the more important the higher the BGA pin count is.
In contrast to the advantages of the BGA packages, prevailing solutions in BGA packages have lagged in performance characteristics such as the ability to maintain signal integrity in high speed operation necessary for devices such as high speed digital signal processors (DSP) and mixed signal products (MSP). One major source of signal distortion derives from irregular, unwanted high-frequency radiation originating in the package substrates; another major source is a specific consequence of a BGA manufacturing method aiming at low-cost package fabrication.
Normally, packages are designed to minimize inductance and capacitance on the signal and clock traces to allow the transmission of waveforms with minimum distortions. An example for BGA packages can be found in U.S. Patent Application Serial No. 60/147,596 filed Aug. 6, 1999 (Lamson et al., xe2x80x9cStructure and Method of High Performance Two Layer Ball Grid Array Substratexe2x80x9d). In some cases, where the signal or clock rise times are fast enough, some radio frequency (rf) radiation will occur in the IC within the package and/or the related circuit board.
Within the confined space of a semiconductor package, there is not enough room to accommodate additional external components, or to assemble a multi-level structure as a low pass filter. The latter idea was proposed in U.S. Pat. No. 5,668,511, issued on Sep. 16, 1997 (Furutani et al., xe2x80x9cLow Pass Filterxe2x80x9d).
The layout of high performance ICs is typically so crowded that silicon real estate cannot be freed up to design the components of a low pass filter. This makes the implementation difficult for integrated solutions as described in U.S. Pat. No. 4,176,318, issued on Dec. 29, 1987 (Koike, xe2x80x9cLow Pass Filter Formed in an Integrated Circuitxe2x80x9d).
BGA substrate fabrication is under economical pressure to keep manufacturing costs to a minimum. Consequently, batch fabrication techniques are preferred, which deposit interconnection lines to the desired thickness on insulating substrates directly xe2x80x9cwhere wantedxe2x80x9d. For metal deposition, a very cost-effective method for batch deposition is plating, provided that it is uniform and controlled. In the BGA substrate fabrication, all lines are electrically coupled together for the period of plating deposition, and separated after completion. When this separation step is executed as a mechanical cut, it is unavoidable that small pieces of metal lines are leftover xe2x80x9cdanglingxe2x80x9d as loose ends. In device operation, these loose ends are available to act as unwanted radiating antennas.
Consequently, a serious device signal distortion problem has arisen in high frequency devices with a need to reduce radiation in the IC. An urgent need has therefore appeared to conceive a concept for avoiding the signal distortion without interfering with the low-cost substrate manufacturing practices. Preferably, this concept should be based on a fundamental design solution flexible enough to be applied for different semiconductor product families and a wide spectrum of design and assembly variations. It should not only meet high electrical and thermal performance requirements, but should also achieve improvements towards the goals of enhanced process yields and device reliability. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
According to the present invention for integrated circuit chip packages, a low pass filter, comprising a network of inductors and capacitors, for removing unwanted high frequency components from fast ramp rate signals and clock lines is provided so that it is integral to the package substrate, located substantially in the substrate region intended for chip attachment, and can be created by a single level of metallization.
A chip output signal with fast rise time (plotted in the form of voltage as a function of time; voltage and time on linear scale) can be subjected to Fourier analysis. The resultant frequency distribution can be analyzed with regard to its energy content (plotted in the form of power as function of frequency; power on exponential scale, frequency linear scale). This output signal power distribution shows a rapid fall-off towards higher frequency.
When chip signals exhibit faster and faster rise times, at constant overall signal power, the output power distribution displays an increase of the power content for higher frequencies. In order to reduce this high frequency power component back to original levels, a low pass filter is added to the IC package design. The invention describes a layout integral to the package substrate without the need for additional individual components or extra metallizations. The design provides passive filtering for fast ramp rate signals and clock lines to remove high frequency components from the transmitted waveform and thus to reduce the power share of the higher frequencies.
It is an aspect of the present invention to use a series connection of narrow and wide traces in the layout of the package substrate to create controlled inductances and capacitances to filter out high frequency components of transmitted signal or clock.
Another aspect of the invention is to provide design concepts suitable for semiconductor package substrates, especially ball grid array substrates, as well as generally for circuit boards. In all cases, the low pass filter is laid out so that it substantially fits into the region allotted to the chip attachment so that not extra substrate area needs to be consumed.
Another aspect of the invention is to provide design concepts for ball grid array substrates applicable to both wire bonded and flip-soldered chip assemblies.
Another aspect of the invention is to use only the standard metallization process flow without the need of additional process steps, multi-level structures, or electronic components, such as external capacitors and inductors, to fabricate the device package. The area requirements of the package substrate, and the thickness constraints of the package do not have to be expanded in order to accommodate the filter network according to the invention.
Another aspect of the invention is to utilize existing semiconductor fabrication processes and to reach the electrical device goals without the cost of equipment changes and new capital investment, by using the installed fabrication equipment.
Another aspect of the invention is to provide design and fabrication solutions such that they are flexible enough to be applied for different semiconductor high-performance device families and a wide spectrum of high speed, high power design and assembly variations.
These aspects have been achieved by the electrical design of the capacitance, inductance, and resistance network for bonding wire assembled IC chips in 144-ball grid array devices. As an example, at 500 MHz the output power has been attenuated from xe2x88x9220 dB to xe2x88x9225 dB. A reduction by 3 or 4 dB is sufficient.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.